Problem: Architecture Superbugs
Parallelism has created an increasing number of superbugs at the system architecture level. Traditionally, verification tasks for system architecture requirements, such as those related to deadlock and cache-coherence, have been undertaken through full-chip RTL simulation or emulation. These methods occur late in the design cycle after all design modules are coded and integrated to construct the entire chip.
The coverage achieved for complex SoCs at this level is predictably low, which leaves the possibility of architectural bugs surviving the verification process.