Design bugs brought about by the megatrend use of parallelism to keep pace with performance and efficiency demands in the wake of Moore’s Law finally have a name: “Simulation-Resistant Superbugs.” The topic of combating these superbugs took center stage with Oski at DAC. Check out our previous blog titled “Simulation-Resistant ‘Superbugs’ Are Here. Time to Rethink Your Verification Strategy.”
Discussions with many of our clients leading up to DAC revealed that the rise of simulation-resistant superbugs affects a wide array of domains including CPU, GPU, networking, wireless, communication protocols, functional safety, and machine learning. No semiconductor and IP sector is immune. The chart below depicts the functional aspects within each domain that are at risk. Take a look to see if your design is vulnerable.
But why are simulation-resistant superbug so dangerous? These superbugs go undetected by simulation and are typically found too late in the game by emulation. Hiding behind each superbug may be clusters of sister superbugs that can set your verification efforts into a tailspin. Trying to find these bugs during late stage emulation leads to unpredictable sign-off and costly re-spins. Often, these superbugs escape to silicon where they are either found in the lab or by an end customer.
To solve these complex verification issues, our world-class team of formal experts developed application-specific formal verification methodologies that zero in on specific application behavior to exhaustively uncover simulation-resistant superbugs with greater efficiency leading to predictable, confident sign-off and higher quality designs.
Combating Superbugs Case Studies
These methodologies were showcased at DAC with a variety of case studies from Cisco, Cavium, Nvidia, and Qualcomm that were presented in our booth and in the DAC Designer Track. To watch full version of the individual case study videos, go to our case study videos page.
Assessing Simulation-Resistant Superbug Risk
Our Oski Formal Experts have the unique ability to assess your design’s vulnerabilities to superbugs. We held many risk assessment meetings at DAC where we rank ordered attendees’ design block by superbug risk. The assessments provided the ability for the engineering teams to identify where and when simulation would be most beneficial and where Oski Formal can be applied to uncover scary superbugs. With the right verification strategy applied, predictable sign-off can be achieved.
If you missed the Superbug Risk Assessment at DAC, you can sign up for a complimentary superbug risk assessment on our web site.
Quest for Greater Superbug Understanding
In an effort to continue our understanding of how simulation-resistant superbugs affect today’s designs, we hosted an Executive Summit during DAC at the famed Scala’s Bistro in San Francisco. The meeting was designed to answer questions about whether or not simulation-resistant superbugs are stifling innovation and how best to combat them.
In attendance were senior executives from top semiconductor and IP companies representing an array of design domains: Farhan Raman from AMD, Charlie Janac from Arteris, Bahman Rabii from Google, Sandeep Bharathi from Intel, Guy Hutchison from Marvell/Cavium, Anshu Nadkami from Nvidia, Samit Chaudhuri from NVXL, Simon Duxbury from Quantenna, Seonil Choi from Samsung.
Vigyan Singhal, Oski’s Founder, and Craig Shirley, Oski CEO, co-facilitated the discussion with Dave Parry, Oski COO, also in attendance.
Brian Bailey from the publication SemiEngineering.com was granted exclusive access to the meeting and will be providing a full write-up of the event in the coming weeks.
Below are questions that helped guide the discussion. How would you answer these questions? Let us know.