Post-Silicon Formal Debug

Problem: Parallelism Increases Post-Silicon Bug Risk

Designers’ architectural advancements are leveraging various forms of parallelism. This gains them the requisite performance specs, while increasing the risk that subtle bugs survive the best efforts of pre-silicon verification, including random simulation, emulation and FPGA prototyping.

Some bugs go undetected in lab testing, and are only discovered in the field, making them even harder to reproduce. Perhaps the bug causes a lock up, where the device becomes partially or fully unresponsive. The bug may occur intermittently, once every few hours or days, making it even harder to resolve.

Oski Post-Silicon Formal Debug Finds Bugs Faster

Oski has successfully resolved dozens of post-silicon bugs for our customers with a turnaround time that is typically less than a quarter of the time required by simulation or emulation methods.

We achieve this fast turnaround time by applying sophisticated formal verification methodologies to quickly reproduce and uncover the root cause of the bug, while ensuring all related bugs are found to avoid additional re-spins. Finally, we quickly validate and sign-off the bug fix(es).

Below is a high-level look at some of formal techniques we deploy.

Post-Silicon Bug Root Cause Identification

Model known bug symptoms

  • Bug symptoms are the design states captured once the bug is triggered.
  • States can be observed using device interrupt & status registers, debug ports & instruction traces & on-chip logic analyzers.
  • Observations can then narrow testing scope to one or a group of design modules.

Formal shows how bug states can be reached

  • Once the bug state is known, we must answer how the design reached that point.
  • Oski’s post-silicon formal debug methodology is very efficient at honing-in on the root cause of the bugs.

Identify system-level bugs & root cause

  • Some post-silicon bugs, such as SoC-level deadlocks, involve the interaction of multiple blocks and on-chip networks
  • In such cases, Oski deploys system-level formal verification to determine the root cause of post-silicon bugs at the chip level.

Validating the Bug Fix(es)

Once the bug is identified, understood, and fixed, the next step is to validate the fix for all possible conditions and ensure that any bugs lurking behind the fix are found before tapeout.

Beyond Post-Silicon Bug-Hunting: Formal Sign-off

Oski frequently works with new customers to quickly solve a post-silicon bug crisis, and subsequently deploys formal sign-off on future projects to ensure first-pass silicon success.