Problem: Parallelism Increases Post-Silicon Bug Risk
Designers’ architectural advancements are leveraging various forms of parallelism. This gains them the requisite performance specs, while increasing the risk that subtle bugs survive the best efforts of pre-silicon verification, including random simulation, emulation and FPGA prototyping.
Some bugs go undetected in lab testing, and are only discovered in the field, making them even harder to reproduce. Perhaps the bug causes a lock up, where the device becomes partially or fully unresponsive. The bug may occur intermittently, once every few hours or days, making it even harder to resolve.