Formal tools and technology have made significant advances in recent years. Formal tools allow designers to more easily use formal, even when formal was not part of the initial verification strategy. This is especially valuable for very large designs, which is why an increasing number of very visible IC companies are adopting formal as part of verification sign-off.
But while formal is being more widely adopted, no formal tools on the market today completely solve the problem of state-space explosion. Even the best high-performance formal tools very rapidly run into complexity and state space explosion and inevitably fail to converge, having a significant and detrimental impact on schedule. For small and medium-sized designs, they may never finish the job because the tools are looking at a very large state space of the design.