Problem: Parallelism & “Superbugs”
The surge in parallelism and functional complexity has led to an increase in insidious bugs that are impossible to find pre-silicon using simulation or traditional formal methods. High-risk blocks with parallel structures, multiple power modes, concurrent processing, and/or multiple operational modes overwhelm simulation and lead to silicon bug escapes.
These blocks have too many combinations to test in simulation to completely cover all temporal relations between events. Additionally, finding one of these “superbugs” is a strong indicator that there are related bugs nearby, making it difficult to predict when all the bugs will be fixed, and the chip will be approved for tape-out.
Superbugs are always root-caused to concurrent logic blocks and never to sequential logic blocks. To restore chip-level, sign-off confidence we need a verification strategy that will predictably close all logic in “project time”:
- Concurrent Logic: formal sign-off methods find all bugs, including bugs caused by parallelism, in these high-risk blocks.
- Sequential Logic: advanced simulation methods can effectively close these blocks.