Formal Sign-Off with Formal Coverage (JUG) 2015

Oski Technology will co-present with ARM at the Jasper User Group Conference October 7 and 8, 2015 at the Cadence San Jose Auditorium, Building 10. The title of the paper is “Formal Sign-Off with Formal Coverage”, and the authors include Vigyan Singhal (Oski Technology),  Ashutosh Prasad  (Oski Technology) and Vikram Khosa (ARM).

Formal verification can replace simulation for block-level verification. In order to achieve this in practice, we need a methodology to demonstrate the completeness of the formal testbench (constraints, checkers and achieved proof depths when proofs are bounded).

Formal coverage is a relatively new advancement that enables the quantification of the completeness of the formal testbench, and progress of the project, with a measurable metric. This presentation discusses a methodology that relies on the JasperGold Design Coverage Verification App to measure formal coverage, and demonstrates how formal coverage (FVCOV) is being used on ARM’s next-generation processor design to plan for and achieve sign-off quality verification on specific design units.

The Jasper User Group Conference is an interactive, in-depth technical conference connecting designers, verification engineers, and engineering managers to share the latest design and verification practices based on Cadence® JasperGold® formal verification technologies and methodologies.

About Oski

Oski Technology is the world’s first and only formal verification services company to successfully leverage off-the-shelf EDA tools with a unique formal verification methodology for the proper integration of formal with simulation and End-to-End Formal verification. Oski has pioneered a new approach with its proprietary Oski Abstraction Models, delivering complete End-to-End Formal verification of even the most complex SOC designs.

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