Design Automation Conference
Jun 3-5, 2019
Las Vegas Convention Ctr.
Oski DAC Booth Theater Presentations. Register today!
Every attendee is automatically entered into a draw for this foldable drone with HD camera.
Formal Sign-off Meets Real-World Tapeout Schedules
How formal verification was used to accelerate the verification process and meet the challenging tapeout deadline for the Surface Write Unit of a GPU.
Monday – 1 pm
Tuesday – 2:30 pm
Wednesday – 4pm
Metrics-Driven Formal Sign-Off of PCIe PCS
A metrics-driven formal verification solution for verifying multi-clock plesiochronous Rx path of PCIe physical layer logical sub-block.
Monday – 4 pm
Tuesday – 1 pm
Wednesday – 11 am
Formal Verification of a Resource Allocator Unit
How formal verification was used to prove that a Resource Allocator Unit correctly processed any combination and sequence of input requests to allocate, update or release resources.
Monday – 2:30 pm
Tuesday – 11 am
Wednesday – 1 pm
Thwarting Inevitable Bug Escapes with Exhaustive Formal Sign-Off
Learn how to 1) predict where your next inevitable bug escape will occur, 2) find all bugs in these high-risk areas, 3) and prove that the last bug has been found. Bug escapes are no longer inevitable.
Monday – 11 am
Tuesday – 4 pm
Wednesday – 2:30 pm
DAC Designer Track Invited Session – Organized by Oski
Monday 1:30pm – 3:00pm | Room N262
5.1 A Novel Approach to PCIe Receiver Framing Checks
5.2 Formal Verification of a GPU Shader Sequencer
5.3 Effective Formal Solutions to CPU Verification Challenges