Wednesday October 28, 2020 15:30 – 16:00 CET
Oski Technology is glad to be back at DVCon Europe this year and to be presenting a case study with u-blox. Verification of deadlocks is one of the biggest challenges faced by many IC design teams across the industry. To learn how formal sign-off methodology solves this challenge, join Emrah Armagan and Roger Sabbagh for their talk on “Discovering Deadlocks in a Memory Controller IP”.
Technical Session Details
Paper 2.4 Discovering Deadlocks in a Memory Controller IP
Jef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach – u-blox AG
Pranay Gupta, Anshul Jain, Chirag Agarwal, Roger Sabbagh – Oski Technology, Inc
Abstract: The risk of deadlocks is one of the areas that is not well addressed by dynamic testing. Simulation does not provide the tools to target deadlocks directly, so finding deadlock scenarios generally happens by chance. On the other hand, formal verification is particularly well suited to verifying a wide range of forward progress properties of designs, such as absence of deadlock, live-lock, and starvation. In this paper, we present a formal verification methodology that has been shown to predictably discover deadlock in RTL designs. The methodology is applicable in the early phases of IP development and design integration. We share results from the application of the method on an industrial memory controller IP