Introduction to Simulation Resistant Superbugs
The Rise of Simulation-Resistant Superbugs
What is Simulation Resistance?
Some designs exhibit a phenomenon called simulation resistance. These are designs for which simulation is unable to reach 100% coverage or find 100% of the bugs within the limits of the project schedule. Fig. 1 shows the typical bug curve for a simulation resistant design. These types of designs obey the 80/20 rule where 80% of the effort is required to achieve the last 20% of the coverage. In these cases, the simulation effort hits a point of diminishing returns where the bug curve levels off and the project comes to an end before the coverage goals are achieved.
Figure 1: Typical simulation-resistant superbug design curve
Why does Simulation Resistance occur?
Silicon designs have reached an unprecedented level of complexity. Moore’s law has slowed and to meet the ever-increasing demand for performance, designers have made architectural advancements that leverage various forms of parallelism. These designs require complicated synchronization and resource sharing techniques that exponentially increases the number of possible states to be tested and raises the risk of bugs being missed in simulation.
What are Simulation-Resistant Superbugs?
Analogous to how antimicrobial resistance in medicine leads to infectious superbugs, simulation resistance leads to silicon superbugs. Simulation-resistant superbugs are bugs that simulation is unlikely to find given the following two practical constraints:
- The challenge of considering all environmental conditions or scenarios
- The time required to test all possible combinations of data and timing of events
What are the symptoms of Superbugs?
Discovery of late stage bugs is usually a worrisome sign that a design contains hidden superbugs. When block-level bugs are found at the system-level by simulation, emulation, prototyping or in silicon, it’s often an indication that the block is simulation resistant. These bugs can be discovered when the system-level stimulus varies in subtle ways so that the range and timing of inputs triggers a previously undiscovered failure of the block. Once one superbug is found, it can lead to the discovery of a cache of related superbugs that are triggered by stimulus that exercises the block in similar ways.
Application Specific Superbugs
Almost every design application has highly complex features and design elements that may contain simulation resistant superbugs. Over time, the most popular design applications have been characterized to predict the areas where superbugs commonly occur, as shown in Fig. 2.
Figure 2: Application domains and their functional areas of superbug vulnerability
For more information, see our applications specific pages.
Formal Verification Targets Application Specific Superbugs
Oski has developed the expertise of using formal verification to target superbugs in specific design applications. Oski has pioneered the Formal Sign-off methodology which uses end-to-end formal checkers and abstraction models to exhaustively test complex designs. In addition, Oski’s innovative architectural formal solution enables the detection of system-level superbugs, such as those related to deadlock and cache coherence. Fig. 3 shows how Oski’s formal verification methodology accelerates bug discovery and deterministically closes the coverage gap.
Figure 3: Oski Formal Verification vs. simulation curves for simulation-resistant superbugs