Upcoming Decoding Formal Club Meeting

Tuesday, September 25, 11:30am – 5pm


The Conference Center
2055 Gateway Place
San Jose, CA

Sponsored by:  

Attendance is complimentary, but space is limited and pre-registration is required (registration link).

AGENDA:

11:30 – Registration and Lunch
1:00 – Presentations
Opening Talk

Leveraging Formal Verification to Combat Simulation-Resistant Superbugs
The Parallelization Megatrend in Modern IC design requires advanced verification strategies to mitigate tapeout delay and bug escape risks. Vigyan shares how to predict the scariest blocks and plan the right verification strategy to address these risks.
Presented by: Vigyan Singhal, Founder and Chief Oski

Case Studies

Formal Verification of a GPU Shader Sequencer
How formal property verification was used to target simulation-resistant and difficult to cover functions of a GPU shader sequencer.
Presented by: Vaibhav Tendulkar, MTS ASIC Engineer, AMD

A Novel Approach to PCIe Receiver Framing Checks
Proving the absence of payload/header data interference in a PCIe Receiver Framer.
Presented by: Guru Karthikeyan, Senior R&D Engineer IC Design, Broadcom

4:00 – Networking Reception

 

What is Decoding Formal?

The Decoding Formal Club is a forum for formal enthusiasts, pioneers, leaders and colleagues who work to promote the sharing of ideas, advancement of formal technology, and adoption of formal sign-off within the industry. More information about past Decoding Formal Club meetings is here, including video and technical presentations, photos and news. Look for updates on our blog.