Discover how semiconductor leaders leverage
Oski's expertise to reduce verification cost and
Oski Technology has used Cadence’s Incisive Formal Verifier (IFV) at many customer projects to enable successful adoption and proliferation of formal technology in customers’ verification flow.
Oski has also used IFV at DAC2012 Verification Challenge where Oski took a NVIDIA design unseen and successfully formal verified it in 72 hours live at DAC and found 4 design bugs.
Oski is also a frequent lecturer in Cadence Club Formal seminars to teach Oski Formal Methodology to IC design & verification communities.
Cadence and Oski’s active collaboration enables broader adoption of Oski’s proven formal methodology so formal verification can become a sign-off criteria.
Oski Technology has used Mentor Graphics’ Questa Formal in many customer projects to find corner case design bugs and deliver high quality IC designs. Successful application of formal technology also helped customers tapeout on or ahead of schedule.
DAC2013 Oski will use Questa Formal in our floor demo to show case the benefits of utilizing abstraction models in formal verification. Formal coverage is also demonstrated.
Active partnership between Mentor and Oski benefits end users to create innovative SoC designs.