Complimentary Block Analysis | Case Studies | Designer Track | Partner Theaters | Application Discussion Sign-Up

Combating Simulation-Resistant Superbugs

Simulation-resistant ‘superbugs’ are on the rise as designers rely on parallelism and concurrency to scale performance and power efficiency in a Post-Moore’s Law Era. These superbugs are typically application specific and affect a broad range of domains including CPUs, GPUs, Networking, Wireless, Functional Safety, and Machine Learning.

Simulation-resistant superbugs typically go undiscovered until very late in the design cycle. Often, they escape to silicon, only to be found in the lab or by an end customer. Superbugs may also hide clusters of sister superbugs, making it even more difficult to predict when verification will be complete and the design is ready for tape-out.

Oski Formal Experts Can Find Your Superbugs

Our formal experts use unique application-specific sign-off methodologies to understand the behavioral details of your design and prove the absence of all bugs, including elusive superbugs. We’ll help you eliminate these superbugs much earlier in the verification process and achieve predictable, efficient, and confident sign-off.

Read more: “Simulation-Resistant ‘Superbugs’ Are Here. Time to Rethink Your Verification Strategy”

Understand your mission critical blocks — Get a Complimentary Superbug Risk Assessment

Sign-up for a Superbug Risk Assessment in our private suite at DAC. The analysis will rank order your blocks by superbug risk.  This enables you to employ the most effective verification strategy to reach predictable sign-off.

Book a time with our experts at DAC >>

Our Clients Share Their Secrets to Combating Simulation-Resistant Superbugs

Oski Theater – Booth #2319

Attendees in the Oski Theater will receive a t-shirt and be entered into a draw for a Flyington Drone.

 

Formal Verification of Software Configurable Silicon for SDN
The configurability of multi-terabit Software Defined Networking devices ushers in a new level of challenge in the verification process. The number of combinations of configuration settings exceeds the practical limits of traditional verification methods. This presentation describes how Oski’s Formal Verification Methodology was used to address this challenge on the Cavium XPliant® Ethernet Switch designs.

 


Formal Verification Methodology for Networking Designs

This talk will describe Cisco’s experience of upskilling and defining a formal verification methodology that works for the complexity of networking chips. Several aspects of implementing a formal methodology will be discussed including flow development, infrastructure and coverage metrics. Lessons and formal techniques learned from Cisco’s experience will be shared.

 


Architectural Formal Verification of System-Level Deadlocks
Architectural formal verification leverages the exhaustive analysis capability of formal to explore all corner cases while also using highly abstract architectural models to overcome complexity barriers and enable deep analysis of design behavior. This powerful combination enables effective system-level requirements verification that is especially useful to target areas that are not well covered by traditional verification methods, such as deadlock.
This presentation provides an architectural formal verification methodology that has been used to verify system-level requirements such as absence of deadlock.

 

Oski Presentation: Superbugs: Leveraging Formal Verification to Combat Simulation-Resistant Bugs

“Superbugs” can survive because of simulation’s inability to test all possible functional scenarios. Simulation coverage closure is difficult and coverage models represent a limited view of the design’s behavior. Critical bugs may go undetected, leaving your design at risk of failure. Oski Formal Methodology with formal coverage closure and abstraction models can be applied to various applications to ensure simulation resistant bugs are vanquished.


Designer Track
Nvidia – “Architectural Formal Verification of a Coherency Manager”
Where: Designer Track Poster Session, Level 2 Exhibit Floor
When: Tuesday, June 26, 5:00 PM to 6:00 PM

Qualcomm – “Formal Signoff Meets Real-World Tapeout Schedules”
Where: Designer Track Presentation, Room 2012
When: Wednesday, June 27, 10:30 AM to 12:00 PM

More Ways to Learn

Join Us in the Mentor Verification Academy
Presentation:
Superbugs: Leveraging Formal Verification to Combat Simulation Resistant Bugs

“Superbugs” can survive because of simulation’s inability to test all possible functional scenarios. Simulation coverage closure is difficult and coverage models represent a limited view of the design’s behavior. Critical bugs may go undetected, leaving your design at risk of failure. Oski Formal methodology with formal coverage closure and abstraction models can be applied to various applications to ensure simulation resistant bugs are vanquished.

When: Tuesday, June 26 4PM
Location: Mentor Verification Academy – Booth #1622

Join Us in the Cadence Theater
Presentation: Architectural Formal Verification of a Coherency Manager – an Nvidia Case Study

Where: Cadence Booth #1308
When: Monday, June 25 10:30AM

Applications and Their Superbugs

Find Out Where Oski Formal Can Help – Get an in depth understanding at our booth #2319.

 

Schedule a 1:1 Application Discussion in Our Booth

Security
captcha