Oski Technology will be exhibiting at booth #2301, DAC 2014 June 2 – 6, 2014, San Francisco, CA
Time: DAC exhibits are open June 2 – 4, 2014
Venue: Oski Booth #2301, Moscone Convention Center, San Francisco California.
Oski will also be participating in the following events at DAC:
- Monday June 02, 1:30pm – 3:00pm: IP Track, Verification: Modeling Xs in Behavioral Models for Hard IPs
- Monday June 02, 1:30pm – 2:15pm: EDA Track, Business: Pavilion Panel: China Fabless: Threat or Opportunity?
- Tuesday June 03, 4:00pm – 6:00pm: EDA Track, Designer/IP: Designer Track: Accelerating Productivity Through Formal and Static Methods
- Wednesday June 4, 2014, 11am: Mentor Verification Academy: Introduction to Formal Sign-off Methodology
- Thursday June 05, 2:00pm – 4:00pm: EDA Track, Verification: DAC Insight: Starting Formal Right from Formal Test Planning
Monday June 02, 1:30pm – 3:00pm | Room 101
Track: IP Topic Area:Verification
Modeling Xs in Behavioral Models for Hard IPs
Speaker: Prashant Aggarwal – Oski Technology, Inc., Mountain View, CA
Authors: Prashant Aggarwal – Oski Technology, Inc., Mountain View, CA
George Curkowicz – Cypress Semiconductor Corp., San Jose, CA
Mark Glasser – NVIDIA Corp., Santa Clara, CA
Vigyan Singhal – Oski Technology, Inc., Mountain View, CA
Monday June 02, 1:30pm – 2:15pm | Booth 313
Track: EDA Topic Area: Business
Pavilion Panel: China Fabless: Threat or Opportunity?
Moderator: Junko Yoshida – EE Times, Madison, WI
Organizer: Thomas Wong – Cadence Design Systems, Inc., San Jose, CA
Limin He – Cadence Design Systems, Inc., San Jose, CA
Jin Zhang – Oski Technology, Inc., Shanghai, China
ShaoJun Wei – Tsinghua Univ., Beijing, China
The 2013 smart phone market was close to 1 billion units. Chinese brands accounted for 50% of the total. 70% of Chinese phones used apps processors and SoCs designed in China or Taiwan. Has the center of gravity of SoC innovation shifted to China? Where is funding available for fabless chip start-ups? Come and find the answers for yourself! Are you ready to pack your bags and head to China or can you still launch your business from Silicon Valley?
Tuesday June 03, 4:00pm – 6:00pm | Room 105
Track: EDA Topic Area: Designer\IP Track
Designer Track: Accelerating Productivity Through Formal and Static Methods
Chair: Vigyan Singhal – Oski Technology, Inc., Mountain View, CA
Formal and static methods, which analyze a design directly rather than depending on large numbers of simulation vectors, are becoming increasingly important in the world of modern design. In the first part of this session, real-world practitioners who have been successful with formal verification describe case studies and use them to supply useful advice for those who wish to achieve similar results. Then we move on to describe some new and powerful uses for static and formal techniques in conjunction with other tools and methods, providing new insights into IP integration, clock domain crossings, power issues, and clock/reset design.
Formal sign-off is a new concept in the industry. Like simulation sign-off, formal sign-off requires a thorough and systematic methodology, which includes End-to-End checkers to verify complete functionality, constraints, Abstraction Models to overcome complexity and coverage to measure results. This talk discusses each component of the formal sign-off methodology so formal can be applied in the verification sign-off flow to maximize efficiency & productivity.
Thursday June 05, 2:00pm – 4:00pm | Room 256
Track: EDA Topic Area: Verification
DAC INSIGHT: Starting Formal Right from Formal Test Planning
Organizer: Jin Zhang – Oski Technology, Inc., Mountain View, CA
Verification planning is key to the success of any verification tasks and this is especially true for formal verification. Formal technology, while it can be very powerful in proving complete functional correctness of designs, is not suited for all design types.
This session discusses the 3 stages of Formal Test Planning – IDENTIFYING the right design blocks for formal verification; ESTIMATING the formal verification effort using key metrics; and PLANNING the actual formal verification tasks on the chosen designs. Through case studies and interactive discussions, audience will walk away knowing how to start formal verification right from Formal Test Planning.
Speakers: Vigyan Singhal – Oski Technology, Inc., Mountain View, CA
Prashant Aggarwal – Oski Technology, Inc., Mountain View, CA
Jin Zhang – Oski Technology, Inc., Mountain View, CA
Oski Technology is the world’s only dedicated formal verification service provider. Oski’s Formal Sign-off Methodology™ uses end-to-end checkers, constraints, Oski Abstraction Models™ and formal coverage metrics to catch corner case bugs, replace simulation for the blocks verified, and improve overall verification efficiency. Oski has provided formal verification services to many leading semiconductor companies including Cisco, Cypress, NVIDIA, Rambus and Xilinx to tape out critical projects, establish formal sign-off methodology and develop customer formal expertise. Oski is a formal sign-off company.
DAC is the largest semiconductor conference in the industry.
Visit Oski Technology at www.oskitechnology.com.