IPB201 (Arteris IP) Architectural Formal Verification of Cache Coherent Protocols

Session Track: IP / Block Verification
Speaker: Kamal Sekhon, Abhinav Nippuleti,
Time: Wednesday, April 11, 9:30am – 10:10am ,
Room: Room 206

Session Description: System level requirements, such as memory coherency, are increasingly being formally verified at the architectural design level. Traditionally, we relied on RTL verification to test these requirements, but the coverage is non-exhaustive and confidence gained at that level is insufficient. Moreover, bugs may be found very late in the design cycle where they risk generating a lot of churn. The complexity of today’s designs dictates that a new approach be taken. This paper describes how we deployed architectural formal verification with design architects very early in the design process, before any RTL code was developed, and the benefits that resulted.