Registration is now closed for the Decoding Formal Feb. 29 meeting at the Santa Clara Marriott Hotel. This meeting is sponsored by Synopsys.
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We’ll be hosting lunch, followed by a panel discussion on where and how to apply formal. What types of designs and blocks are great candidates for formal verification? Which methodologies work best? Should formal work be undertaken within the design or verification team, or delivered by a centralized formal verification team? Roger Sabbagh, Ashish Darbish, Stuart Hoad and Normando Montecillo will discuss with moderator Brian Bailey the factors they consider when evaluating the case for formal.
Oski engineer Anshul Jain will discuss the results of the 2016 Oski Formal Puzzler Chessboard Challenge and the winner will be announced! Oski’s CEO Vigyan Singhal will also conclude with a presentation on formal coverage.
11:30 AM Lunch, Networking and Welcome
12:30 PM Panel: “Where and How to Apply Formal Verification”
Moderator: Brian Bailey, Technical Editor, Semiconductor Engineering
Panelists: Ashish Darbari, Principal Engineer, Imagination,
Stuart Hoad, Lead Engineer, PMC Sierra (now Microsemi),
Normando Montecillo, Associate Technical Director, Broadcom,
Roger Sabbagh, Principal Engineer, Huawei
1:30 PM CheckMate: Results from the 2016 Oski Formal Puzzler Chessboard Challenge
Anshul Jain, Engineer, Oski Technology
2:15 PM Awards Ceremony
2:30 PM Coffee & Networking
2:45 PM Formal Coverage
Vigyan Singhal, CEO, Oski Technology
3:45 PM Wrap-up and Prize Drawing
4:00 PM Closing
This event is sponsored by Synopsys
Brian Bailey is a veteran of EDA, having been involved in functional verification since the early 80s. He is primarily an engineer and has been involved in many advances in the fields of simulation and emulation. More recently he spends his time writing about the technology for Semiconductor Engineering and helping startups navigate their way through the EDA industry.
Ashish Darbari leads the Advanced Verification Methodology (AVM) Group in Imagination Technologies where he is pioneering the adoption of formal across all business units worldwide. Dr. Darbari has several papers & patents and is a Fellow of IETE, Fellow BCS, and Senior Member IEEE and ACM. He is also a “Royal Academy of Engineering Visiting Professor” at the University of Southampton, England.
Stuart Hoad is a member of the Platform Architecture Group at Microsemi (previously PMC Sierra), responsible for formal methods architecture and strategy. He started working with formal methods targeting verification of multi-processors and coherency schemes, before moving into research to look at architectural and micro-architectural application, then to PMC Sierra to develop and deploy integrated formal methodologies. Hoad graduated from Loughborough University with a BSc (Hons. First Class) degree in Electronic, Computer, and Systems Engineering, and is a UK Chartered Engineer.
Normando Montecillo is an Associate Technical Director at Broadcom LTD in the set top box division. Normando has a BSEE from Oregon State University. He has been with Broadcom for 18 years, starting out as a design engineer and later focusing on formal verification. Normando is now in charge of the DV team in the set top box group where his group is defining the verification flow in areas of mix signal, UVM, and formal verification. Outside of work, Normando is an aspiring pilot, he currently has logged 100 hours in a Cessna 172 and plan to move on to train on bigger and faster planes. Normando is also an avid guitar player and musician.
Roger Sabbagh is the formal verification team leader at Huawei, Canada. He is a 25+ year ASIC industry veteran, with experience in design, verification and EDA. Prior to this, Roger held various positions at Mentor and 0-In where he helped scores of design teams to adopt formal methods. When he is not working on formal verification, he enjoys playing, coaching and watching ice hockey.
Vigyan Singhal is President and CEO of Oski Technology, and a regular speaker at the Decoding Formal Club, an open forum welcoming formal verification enthusiasts. Vigyan has worked in the semiconductor and EDA industries for more than 20 years, and founded two venture-funded start-ups – Jasper (acquired by Cadence) and Elastix (acquired by eSilicon). Vigyan began his career with Cadence Berkeley Labs as a Research Scientist. He has authored more than 70 publications, three of which won best paper awards. Vigyan has a PhD in EECS from the University of California at Berkeley where he was a Regents Scholar, and has a BTech in Computer Science from IIT Kanpur where he graduated at the top of his class.