Formal Sign-off Methodology

ARM

What Can Be Learned from Arm’s Implementation of Formal Sign-off

At Oski, we’ve embedded ourselves in the world of Formal verification because we truly believe in the exhaustive nature of Formal to achieve significant confidence in design and verification sign-off.  So, it doesn’t surprise me that Arm’s initial experience with Formal compelled them to employ a much deeper Formal sign-off strategy with their latest design.  …

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Another Reason to Stay an Extra Day in Austin

If you are attending the Design Automation Conference (DAC) in Austin, Texas, June 5-9, and need a good reason to stay an extra day, look no further. Oski Technology is offering a one-day primer on advanced formal verification techniques at the DAC Decoding Formal one-day training, “Achieving Formal Sign-off”, on Thursday, June 9, from 10 a.m. until 5 p.m. at the …

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Achieving Formal Sign-off: Key Learnings for Trainees and Experts

Formal sign-off is possible with today’s technology and methodology. But to get to formal sign-off takes an understanding of what is possible with formal verification, and an immersion in ongoing practice with formal methods and techniques. Moreover, early experiences with formal can determine later success with formal verification and sign-off. Even with a deep knowledge …

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The Perils of Aiming Low: How Management Expectations Can Shape Formal Engineers’ Learning and Performance

I recently read a blog written by Dr. Noa Kageyama, performance psychologist and Juilliard alumnus and faculty member, titled “The Perils of Aiming Low: How Our Expectations Can Shape Our Students’ Learning & Performance.” Based on research findings from schools and sports, Dr. Kageyama concluded that high expectations from teachers and coaches correlate positively with …

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Making the Case to Executives for Formal Verification

Last year, after my presentation to a customer in Asia, the verification manager said, “You should give this talk to our senior executives, so they understand the benefits of formal.” It was said in a lighthearted manner, but in reality it rang true. Design and verification engineers and their managers understand the value of formal. …

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Formal Verification, by Everyone and for Everyone

You might still be skeptical of the idea that formal verification can be used by everyone. After all, there is a deep-rooted perception in the industry that formal verification is for the elite few formal experts with Ph.Ds. This might have been true in the early days of formal technology. The formal tools’ capacity was limited and the …

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Using Formal for Functional Coverage

Brian Bailey’s recent article on “Fixing Functional Coverage” in Semiconductor Engineering (http://semiengineering.com/fixing-functional-coverage/) polled experts from different companies about the challenges of catching all the bugs, utilizing assertions and expanding coverage to the entire system. This blog elaborates on the four points we made in Brian’s article about how formal can help with functional coverage. Hitting …

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Debate over Formal Sign-off vs. Bug-hunting

Formal technologies have been used in many different ways in the industry including automatic formal, formal apps and so on. One of ways of using formal technology is use it for formal sign-off. Oski has developed a Formal Sign-off methodology that covers complete design functionality to ensure 100% correct design behavior according to design spec. …

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How Long Does It Take to Formally Verify This Design?

This year at DAC, we asked attendees to participate in a guessing game – make an educated guess about how long it takes to formally verify a design based on the given design description and statistics. Here is a recap of the information provided to participants: Design Description Reorder IP packets that can arrive out …

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Oski Receives DVCon “Honorable Mention” for Best Paper Bounded Proofs

DVCon 2014 was a successful show for Oski Technology. Not only were we proud to receive an “Honorable Mention” for (2nd) Best Paper at DVCon “Sign-off with Bounded Formal Verification Proofs”, we had the opportunity to have many meaningful conversations with existing customers and others new to formal verification and eager to learn more about …

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The Abstraction Model – Is It More, Is It Less?

Oski Technology provides formal verification services to leading semiconductor companies to verify complex design blocks that are difficult to verify using simulation. In our projects, we often write Abstraction Models to overcome formal complexity barriers that would otherwise render formal verification results inconclusive. For example, for the open-source Sun OpenSparc T1 design, verifying a data …

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Oski Innovation Enables Formal Sign-Off ™ in 2013

A busy year is drawing to a close for Oski Technology. Reflecting back on this year we are proud of what we have accomplished for our valued customers. Oski Formal Sign-Off ™ Methodology, incorporating End-to-End checkers, Abstraction Models and formal coverage – this is the boldest application of formal technology for RTL functional verification. Gone …

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Promoting Formal Education: Oski Shares Experiences at FMCAD 2013

Although Oski Technology is first and foremost a formal verification service company, making effective use of formal tools and promoting education around the power of formal technology has always been at the core of our business. Since Oski was founded in 2005, we have engaged in many activities to help increase the adoption of formal …

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Oski Technology to Showcase Formal Sign-Off Methodology At Verify 2013

Oski Technology will highlight the company’s formal verification success using its powerful and unique Formal Sign-off methodology at Verify2013. Verify2013 is the only professional seminar in Japan to focus on the latest in design verification technology. This is the 14th Verify event, and with 12 exhibitors, Verify2013 expected to draw 200 attendees with customer/vendor presentations …

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IP Customers Beware! “Silicon Proven” IP May Not Be Fully Verified

The verification of all configurations (reaching in millions) of an (silicon) IP is a challenge. I have experienced this problem first-hand both from the vendor side as an embedded SRAM (eSRAM) compiler designer, and from the customer side, as an architect of a wireless SoC using 3rd party IPs. When I was eSRAM compiler designer, …

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On the Practice of Formal Verification

Many tools for end-to-end verification are powerful and productive. Yet the practice of formal verification of hardware RTL designs is mystifying: there are more builders of tools than full-time dedicated users of such tools. Surprising perhaps, except that few places teach the practical application of formal verification. This blog is dedicated to formal verification and …

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Formal vs. Simulation Testbenches: Architecting for End-to-End Verification

In this post we discuss the differences and similarities between the architecture of formal and simulation testbenches. Many organizations are using formal verification as a supplement to existing simulation efforts. Internal design assertions or interface assertions are often ad-hoc, and form the list of checks being verified. Corner-case bugs can be detected with such efforts, …

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Leveraging your Investment in Formal with Abstraction Models

Formal tools and technology have made significant advances in recent years. Formal tools allow designers to more easily use formal, even when formal was not part of the initial verification strategy. This is especially valuable for very large designs, which is why an increasing number of very visible IC companies are adopting formal as part …

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