Simulation Verification Engineer

Job Description:

Candidate will be responsible for creating leading-edge constrained-random verification environments and using them to drive functional correctness of innovative digital design/IP blocks and SoCs. Candidate must be able to take ownership of the full verification life-cycle for a design; developing a robust test plan, executing it by working with the design team and coordinating with other verification team members, requesting prompt support if needed, and driving to coverage closure within schedule constraints. Candidate should also be able to train and lead set of junior engineers for a given verification assignment.

Requirements:

  • 5 to 15 (or more) years of relevant industry experience in ASIC verification
  • Strong educational background with a BS, MS or PhD in CS/EE or equivalent degree
  • Experience with Verilog and SystemVerilog
  • Experienced in UVM-based verification methodologies and assertion-based verification
  • Clear understanding of coverage-driven constrained-random verification process
  • Experience with revision control methodology/systems such as RCS, GIT, SVN, etc. and ASIC front-end process
  • Proficient Linux user with experience in at least one programming language like C, C++ or Java and one scripting language like Perl or Python for verification and verification process automation
  • Experience with TCL
  • Experience with on-chip bus protocols like ACE, AHB, AXI etc.
  • Willingness to work flexible hours to coordinate with US-based development teams

Good to have, but not necessary:

  • Domain knowledge of wireless networking protocols such as 802.11ax, and experience with design/verification of modems implementing them
  • Experience with accelerators and security/cryptographic algorithms like SHA, AES etc.
  • Experience with networking designs
  • Experience with gate-level simulation and/or low power verification methodologies
  • Advanced knowledge of CPU, GPU and SoC architecture/design
  • Working knowledge of academic or commercial formal verification tools.

Candidate must be a team player with excellent problem-solving and communication skills and possess a burning desire to take on new and diverse challenges.

Senior Verification Engineer (San Jose, California)

Job Description:

The position requires application of best-in-class formal methods and formal verification methodology on large, complex ICs, using commercial coverage-driven simulation and formal verification tools. Candidates must be able to learn state-of-the-art verification concepts and methodology, and apply these in an advanced verification setting.

Requirements:

  • Strong educational background with a BS/MS/PhD in Computer Science, or experience in developing modular software or hardware components.
  • Experience in developing simulation‐ or formal‐based verification.
  • Familiarity with the ASIC design and verification flow.
  • Exceptional problem-solving skills.
  • Good communication and inter‐personal skills.

Desirable, but not required:

  • Working knowledge of academic or commercial formal verification tools.
  • Working knowledge of SystemVerilog, Vera or e verification languages.
  • Knowledge of assertion languages: PSL or SVA.

Verification Engineers (Gurgaon, India)

Job Description:

The position requires learning and applying modern verification tools on IC designs.

Requirements:

  • Strong educational background with a BTech in Computer Science or Electrical Engineering from an IIT, or an equivalent college.
  • 0-2 years of work experience.
  • Exceptional problem-solving skills.

Desirable, but not required:

  • Familiarity with the ASIC design and verification flow.

Oski Technology is an Equal Opportunity Employer, and offers a standard vacations and benefits package. Please e-mail resume to jobs@oskitech.com

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