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Simulation-Resistant Superbugs – A Central Theme of Discussion at DAC

Simulation-Resistant Superbugs – A Central Theme of Discussion at DAC

Design bugs brought about by the megatrend use of parallelism to keep pace with performance and efficiency demands in the wake of Moore’s Law finally have a name: “Simulation-Resistant Superbugs.” The topic of combating these superbugs took center stage with Oski at DAC. Check out our previous blog titled “Simulation-Resistant ‘Superbugs’ Are Here. Time to Rethink …

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Simulation-Resistant ‘Superbugs’ Are Here. Time to Rethink Your Verification Strategy.

Simulation-Resistant ‘Superbugs’ Are Here. Time to Rethink Your Verification Strategy.

Simulation-resistant superbugs are on the rise and wreaking havoc in an array of design domains including CPUs, GPUs, networking, wireless, functional safety, and machine learning. These functional superbugs are resistant to simulation because extreme corner cases are required to activate and detect them. They are a side-effect of designer innovations in parallelism and concurrency to …

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The ABCs of Winning at the 2017 Hardware Model Checking Competition

The ABCs of Winning at the 2017 Hardware Model Checking Competition

Every year for the last nine years teams of researchers and software developers have come together to compete in the Hardware Model Checking Competition (HWMCC). This contest pits some of the brightest minds in design and verification against each other along with the solvers they have developed. Each team has worked tirelessly over the course …

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Implementation of an Architectural Formal Verification Methodology by ArterisIP

Implementation of an Architectural Formal Verification Methodology by ArterisIP

Chances are you’re probably reading this blog post on a mobile device with the utmost confidence that it is doing what you intend it to do.  As consumers, we place a lot of demands on not only our mobile gadgets but also the rest of our personal electronics.  We want them to perform all sorts …

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