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Decoding Formal Club Meeting
Featuring Formal Talks by Barefoot Networks, Cavium, and Qualcomm.
Thursday, December 7, 11:30am – 5pm
The Conference Center
2055 Gateway Place
San Jose, CA
Attendance is complimentary, but space is limited, and pre-registration is required (registration link).
11:30 – Registration and Lunch
1:00 – Barefoot Networks
2:10 – Cavium
3:00 – Qualcomm
4:00 – Networking Reception
Challenges in High Performance Networking Silicon Verification–
Presented by Dan Lenoski, Senior Vice President of Engineering and Co-founder, Barefoot Networks
When designing the Company’s industry changing P-4 programmable Ethernet switch with its leading-edge programmable forward plane technology, Barefoot Networks had to overcome significant verification challenges that forced them to adopt best-of-breed techniques including Formal verification. This presentation outlines those challenges along with the solutions and methodologies that helped to overcome them.
Methodology for Formally Verifying Software Defined Networking Silicon — Presented by Saurabh Shrivastava from Cavium
The configurability of SDN silicon switches ushers in a new level of challenge in the verification process. Formal verification’s exhaustive nature is well-suited to address these challenges and plays a very important role in the verification process of SDN silicon. To that end, this presentation explains a how a Formal methodology was successfully implemented on the Cavium XPliant® Ethernet Switch CNX880xx product family.
A Case Study on Handling System-Level Deadlock Using Architectural Formal Verification — Presented by Mandar Munishwar, Sr. Staff Engineering from Qualcomm
Architectural formal verification leverages the exhaustive analysis capability of formal to explore all corner cases while also using highly abstract architectural models to overcome complexity barriers and enable deep analysis of design behavior. This powerful combination enables effective system-level requirements verification that is especially useful to target areas that are not well covered by traditional verification methods, such as deadlock.
This presentation provides an architectural formal verification methodology that has been used to verify system-level requirements such as absence of deadlock.
The Decoding Formal Club is a forum for formal enthusiasts, pioneers, leaders and colleagues who work to promote the sharing of ideas, advancement of formal technology, and adoption of formal sign-off within the industry. More information about past Decoding Formal Club meetings is here, including video and technical