Register today: Decoding Formal Lunch Meeting, Oct 11

You’re Invited!
Decoding Formal Club Meeting  
Featuring Formal Talks by AMD, Qualcomm and Oski Technology
Tuesday, Oct. 11, 11:30am – 4pm 

Parcel 104 Restaurant, Santa Clara Marriott Hotel

Sponsored by Synopsys

Attendance is complimentary, but space is limited, and pre-registration is required (registration link).  

11:30 AM     Sign-In and Welcome
11:45 AM     Lunch and Networking
 
1:00 PM      “Verifying Datapath for an AMD Processor”
                      Ankit Saxena, Oski                                                                
                      Joint Work with S. Gurumurthy, AMD; F. Rahman, AMD;
                      A. Prasad, Oski
 
2:00 PM       “Mutation and Proof Core: Two Sides of the Same Coin”
                       Mandar Munishwar, Qualcomm
 
3:00 PM       “Formal Verification for Networking Blocks”
                        Vigyan Singhal, Oski
 
4:00 PM         Closing

The Decoding Formal Club is a forum for formal enthusiasts, pioneers, leaders and colleagues who work to promote the sharing of ideas, advancement of formal technology, and adoption of formal sign-off within the industry.  More information about past Decoding Formal Club meetings is here, including video and technical presentations, photos and news. Look for updates on our blog

Press Releases

Barefoot Networks Turns to Oski for Formal Verification Expertise, Sept, 2016
Oski Technology to Showcase End-to-End Formal Verification at DVCon 2016, Feb, 2016
Decoding Formal Club Hosted by Oski Technology Will Feature Panel of Formal Experts, Checkmate Session, Formal Coverage Presentation, Feb, 2016

Blogs

Formal Verification Program Leader: An Emerging Role in Verification Feb, 2016
Oski Holiday Challenge: Fun Formal Puzzler Dec, 2015
Formal 2025: It’s Back to the Future! Oct, 2015
Close Win in Oski Deep Bounds 2015 Hardware Model Checking Competion for Norbert Manthey of TU, Dresden Sep, 2015
Happy Birthday, Decoding Formal! Sep, 2015
Formal Ensures Tight Working Relationships Sep, 2015

Video Tutorials: Decoding Formal Club

Video: Formal Coverage, Chessboard Challenge
Video: Completeness of End-to-End Formal 
Video: Constraint Management for Formal Sign-Off
Video: Formal Sign-Off with End-to-End Checkers
Video: Formal Test Planning for Sign-Off
Video: Using Bounded Proofs in Formal Sign-Off
Video: How to Formally Verify – and Reuse – Highly Configurable IP Designs
Video: How to Achieve Early Formal Convergence with Oski Abstraction Models
Video: How to Know When a Formal Testbench is Complete

Video Interviews and Presentations 

Video: DAC 2016 Interview with Oski CEO, Vigyan Singhal 

Video: Oski Technology “Break the Testbench” Challenge* DAC 2015, Oski’s highly successful “Break the Testbench” Challenge at DAC proved the End-to-End formal testbench is complete and can be used for formal sign-off. 73 functional bugs were inserted by DAC attendees and all bugs were caught, proving the concept that the End-to-End testbench is complete, and that formal verification can be used for formal sign-off.

Video: SA Panel Discussion: IP Verification (Q3 2015), Vigyan Singhal, CEO Oski Technology: IP Verification at the Global Semiconductor Alliance IP Working Group, Q3 Meeting at Rambus, in Mountain View, CA.

Video: DAC 2015 Verification Academy – Starting Formal Right from Formal Test Planning, Jin Zhang, VP of Marketing and Customer Relations

Video: Take 5 with Warren: Vigyan Singhal, CEO Oski Technology, talks with Warren about the strong value proposition for formal verification, the challenge for every large semiconductor company of developing formal expertise in-house, the productivity gains of shifting left and the recognition that without formal verification, the design process is less effective and less productive, and that without it, companies cannot compete.

Technical Papers

Looking for Oski’s award-winning technical papers? You can download these and more, directly from our web site.

  • The Process and Proof for Formal Sign-Off: A Live Study (DVCON 2016)
  • Compositional Reasoning Gotchas in Practice (FMCAD 2015) 
  • Creative Formal Techniques to Verify PCache (DAC)
  • Modeling Xs in Behavioral Models of Hard IPs (DAC) 
  • Sign-off with Bounded Formal Verification Proofs (DVCon, 2nd BEST PAPER AWARD)
  • Deploying Model Checking for Bypass Verification (DAC, BEST PAPER AWARD);
  • Liveness vs Safety; A Practical Viewpoint (HVC) 
  • End-to-End Formal using Abstractions to Maximize Coverage (FMCAD) 
  • How Formal Methodology Shrank the Verification Schedule of a Complex Statistics Block by 6x (DAC) 
  • Guidelines for Creating a Formal Verification Testplan (DVCon, BEST PAPER AWARD)

Articles 

Verification Choices: Formal, Simulation, Emulation, Chip Design, July 21, 2016
Formal Confusion, SemiconductorEngineering, May 26, 2016
A Formal Transformation, SemiconductorEngineering, Mar 24, 2016
Getting Formal About Debug, SemiconductorEngineering, Feb 25, 2016
DeepChip: Hogan on Cadence, Mentor, OneSpin, Synopsys Formal, DeepChip, Feb 18, 2016
Debug Becomes a Bigger Problem, SemiconductorEngineering, Feb 11, 2016
Debug: Last Bastion of Automation, SemiconductorEngineering, Jan 27, 2016
Predictions for 2016: Markets, SemiconductorEngineering, Jan 14, 2016
Verification Grows Up, Verification Horizons, Dec 22, 2015
Minimizing Constraints to Debug Vacuous Proofs, Verification Horizons, Nov 19, 2015
Oski Technology: Formal celebrates its Place at the Table, EDACafe, Nov 9, 2015
HW Vs. SW: Who’s Leading Whom?, SemiconductorEngineering, Oct 29, 2015
The Secret Decoder Ring for Formal Analysis, EDACafe, Oct 28, 2015
Deepchip: Oski on how to do sign off with bounded (incomplete) formal proofs, DeepChip, Oct 8, 2015
Design and Verification Need a Closer Relationship, Chip Design, Aug 19, 2015
Starting Formal Right from Formal Test Planning, Mentor Graphics, Jun 30, 2015

Please subscribe to our newsletter, and check our blog for information about upcoming meetings and events.

The Oski Technology Team 

 

Oski Technology | www.oskitechnology.com

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